Job Duties:
- Lead the physical design team to provide design services to the Semiconductor companies and work on semiconductor chips.
- Develop and maintain physical design flow/methodologies and infrastructure in collaboration with design automation, product engineering and EDA teams to enhance the automated flow.
- Work at a senior level and responsible for all aspects of physical design of semiconductor chips. Participate in establishing physical design methodologies, flow automation, chip floorplan, power/clock.
- Responsible for working in lower nodes – 16nm, 7nm and 5nm. Set direction and strategy for junior team members. Craft designs for static timing analysis, power and noise analysis and back-end verification.
- Work in the lead role and responsible for developing and designing IO ring creation, placement and bump-RDL routing.
- Responsible for floor planning, power planning, placement, clock tree synthesis and routing for blocks and fullchip.
- Responsible for doing sign off STA in multiple modes and corner along with signoff physical and formal verification
- Responsible for power grid integrity and IR/EM signoff.
- Develop and create low power UPF based designs. Provide guidance and direction to junior physical design engineers as required.
- The products on which the incumbent for this position would work includes semiconductor chips. Petitioner is a design services company and supports top tier semiconductor companies in their chip design.
Work Time: Monday to Friday; 8:30 am to 5:30 pm. 40 hours/week.
Salary: $177,341 to 187,341per annum.
Job entails working with and requires Bachelor’s in Electronics Engineering, Electrical Engineering, Telecommunications Engineering, Hardware Engineering, Computer Engineering, Information Technology, or equivalent degree with 5 years of experience including: Complex Design Implementation, Low Power Design, Verification of the Design, Methodology Development, Flow & Scripting.
Employer will accept any suitable combination of education, training or experience. This should be read to mean that the employer requires Bachelor’s in Electronics Engineering, Electrical Engineering, Telecommunications Engineering, Hardware Engineering, Computer Engineering, Information Technology, or equivalent with 5 years of experience in the job offered, Physical Design Engineer, Electronics Engineer, STA Engineer, Design Engineer Manager, Hardware Engineer, or Equivalent.
Travel and relocation to unanticipated places within United States is possible.
To apply please mention Job Code S06 and mail resumes to: Rosheni Fernando, Director of Finance and Administration, Synapse Design Automation Inc., 2200 Laurelwood Road, Santa Clara, CA 95054.