• Looking for experienced engineers in the areas of SW Modeling of Hardware, C++/Assembly Test.
• Job Description: The candidate will be responsible for definition, implementation, debug, and maintenance of CPU architecture verification test suites utilizing extensive Assembly and C level code and interfacing into a System Verilog simulation environment. This person must interface with designers and micro-architects for ensuring coverage goals are established and realized. Test design will span multiple levels of system hierarchy running on a custom 64-bit RISC supercomputer.
• The candidate will be writing assembly/C code using the processor ISA (Instruction Set Architecture) to verify the processor itself.

• 5+ years’ experience completing layouts of high pin count, multi-layer organic build-up packages using Cadence APD and SiP package design tools.
• Creating die and BGA symbols from scratch or from spreadsheet inputs
• Setting up design environment, including tech files, stack ups, and constraints
• Setting up Constraint Manager from scratch for complex packages (diff pair creaton, multiple power supplies, net and zone specific constraints.
• Routing signals and matching length both manually and using tool features
• Design file management and documentation from initiation to final signoff
• Generation of POD
• Solid knowledge of top package suppliers design rules and basic manufacturing practices
• Desired experience
• Experience with Cadence Orbit I/O
• 2.5D interposer design layout experience using Cadence SiP
• Experience with Virtuoso and/or Innovus for 2.5D interposer design
• Experience with Synopsys tools for 2.5D interposer design
• Experience writing and implementing custom scripts in Cadence tools
• Familiar with Cadence PVS

• Design formal verification testbenches for FPGAs for commercial and military.
• Define verification test approach and develop simulation framework
• Document simulation procedures, and verification results
• Review requirements, conceptual design, trade off studies, and design implementation
• Perform for credit testing
• Perform functional tests and design verification tests
• Oversee efforts and train less experienced designers

• Bachelor’s degree and 8 years of prior relevant experience OR
• Advanced Degree in a related field and minimum 5 years’ experience OR
• In absence of a degree, 12 years of relevant experience is required
• Engineering/Other Technical Positions: Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 8 years of prior relevant experience unless prohibited by local laws/regulations
• Must be a U.S. Citizen
• Advanced skills with formal FPGA Verification in a process-controlled environment

• Digital Board Design experience a plus but not required
• VHDL
• UVM
• System Verilog

Please send your profiles to : mike@synapse-da.com

• Implement algorithm blocks as RTL code as defined in the Micro Architecture
• Support DV team for verification of blocks
• Assist with synthesis and timing closure
• Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and
• Primetime is required. 
• Preferred Qualifications 10+ years of experience in SoC design
• Support handoff and integration of blocks into larger SOC environments
• Ability to document and communicate clearly

• Develop and implement test/verification plans, methodologies and tool flows for graphics/display IPs
• Define and implement IP/SubSystem verification plans, test benches and simulation/emulation coverage leading to fully functional IPs/SubSystems/SoCs
• Drive DV plan development and execution through post-silicon bringup/validation
• Define and implement system/integration tests
• Work with cross functional teams to identify best verification methodology
• Build or leverage highly automated & flexible DV environments/flows spanning prototypes, SoC’s and hardware emulation platforms
• Support integration of IP block tests into larger SubSystem or SoC environment tests

• 5+ years of similar experience in Design Verification using System Verilog
• Experience with SystemVerilog UVM testbenches, coverage analysis, and SVA
• Experience with FPGA and SoC design flows, tools and methodology
• Experience with industry standard RTL simulators, emulators and waveform debugging tools
• Capable of dealing with ambiguity with a fast changing consumer electronics field.
• Results oriented, self-motivated, proactive with demonstrated creative & critical thinking

• Verilog/System Verilog experience is must.
• Experience with AMBA Bus protocol (AXI/AHB/APB) is must.
• Experience with Front End tools (simulation, lint, cdc) is required
• Experience with image/Video processing is desirable.
• Experience with Datapath/control logic is desirable.
• Ability to quickly provide simulation debug support
• Good scripting skills is desirable.

• Experience with Hierarchical DFT Architecture
• Experience using Synopsys or Mentor test tools.
• Experience in Scan Insertion, test Muxing, ATPG, MBist & pre/post-layout simulation
• Expertise in Top Level DFT switching with DFT Architecture experience will add value
• Expertise in test clock strategy & muxing required
• Expertise in test timing constraints for shift, capture, mbist or any special mode & timing closure for these modes
• Familiar with low power testability, state tables, and components (LS, ISO, RET)
• Familiar with JTAG for board level interconnect testing
• Programming experience in Tcl & Perl is must
• Involvement in flow development is a plus

• Lead the physical design team to provide design services to the Semiconductor companies and work on semiconductor chips.
• Develop and maintain physical design flow/methodologies and infrastructure in collaboration with design automation, product engineering and EDA teams to enhance the automated flow.
• Work at a senior level and responsible for all aspects of physical design of semiconductor chips. Participate in establishing physical design methodologies, flow automation, chip floorplan, power/clock.
• Responsible for working in lower nodes – 16nm, 7nm and 5nm. Set direction and strategy for junior team members. Craft designs for static timing analysis, power and noise analysis and back-end verification.
• Work in the lead role and responsible for developing and designing IO ring creation, placement and bump-RDL routing.
• Responsible for floor planning, power planning, placement, clock tree synthesis and routing for blocks and fullchip.
• Responsible for doing sign off STA in multiple modes and corner along with signoff physical and formal verification
• Responsible for power grid integrity and IR/EM signoff.
• Develop and create low power UPF based designs. Provide guidance and direction to junior physical design engineers as required.
• The products on which the incumbent for this position would work includes semiconductor chips. Petitioner is a design services company and supports top tier semiconductor companies in their chip design.