The leading SOC and ASIC design services company
Current Openings

Browse through the current openings at Synapse Design and apply. Post your resumes in easy steps to join the Synapse Design team and be agent of innovation.

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Software Test Engineer

Post date :11/16/2022
Job Duties:
Custom CPU
US Citizen
Start immediate:
  • Looking for experienced engineers in the areas of SW Modeling of Hardware, C++/Assembly Test.
  • Job Description: The candidate will be responsible for definition, implementation, debug, and maintenance of CPU architecture verification test suites utilizing extensive Assembly and C level code and interfacing into a System Verilog simulation environment. This person must interface with designers and micro-architects for ensuring coverage goals are established and realized. Test design will span multiple levels of system hierarchy running on a custom 64-bit RISC supercomputer.
  • The candidate will be writing assembly/C code using the processor ISA (Instruction Set Architecture) to verify the processor itself.
Contact :
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Packaging engineer

Post date :11/16/2022
Job Duties:
Sunnyvale CA
  • 5+ years’ experience completing layouts of high pin count, multi-layer organic build-up packages using Cadence APD and SiP package design tools.
  • Creating die and BGA symbols from scratch or from spreadsheet inputs
  • Setting up design environment, including tech files, stack ups, and constraints
  • Setting up Constraint Manager from scratch for complex packages (diff pair creaton, multiple power supplies, net and zone specific constraints.
  • Routing signals and matching length both manually and using tool features
  • Design file management and documentation from initiation to final signoff
  • Generation of POD
  • Solid knowledge of top package suppliers design rules and basic manufacturing practices
  • Desired experience
  • Experience with Cadence Orbit I/O
  • 2.5D interposer design layout experience using Cadence SiP
  • Experience with Virtuoso and/or Innovus for 2.5D interposer design
  • Experience with Synopsys tools for 2.5D interposer design
  • Experience writing and implementing custom scripts in Cadence tools
  • Familiar with Cadence PVS
Contact :
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FPGA Design Verification Engineer

Post date :11/15/2022
Job Duties:
This remote position requires responsibility for all aspects of the formal verification beginning with requirements review up and through the certification of the product. Support of projects includes schedule preparation and reporting of status on assigned tasks as well as interaction with team members from other disciplines. This position will work with little or no supervision.
Primary Responsibilities:
  • Design formal verification testbenches for FPGAs for commercial and military.
  • Define verification test approach and develop simulation framework
  • Document simulation procedures, and verification results
  • Review requirements, conceptual design, trade off studies, and design implementation
  • Perform for credit testing
  • Perform functional tests and design verification tests
  • Oversee efforts and train less experienced designers
Basic Qualifications:
  • Bachelor’s degree and 8 years of prior relevant experience OR
  • Advanced Degree in a related field and minimum 5 years’ experience OR
  • In absence of a degree, 12 years of relevant experience is required
  • Engineering/Other Technical Positions: Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 8 years of prior relevant experience unless prohibited by local laws/regulations
  • Must be a U.S. Citizen
  • Advanced skills with formal FPGA Verification in a process-controlled environment
Preferred Qualifications:
  • Digital Board Design experience a plus but not required
  • VHDL
  • UVM
  • System Verilog
Contact :

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Senior RTL Design Engineer

Post date :11/16/2022
Job Duties:
Senior RTL Design Engineer
Join the Synapse Design group as a Senior RTL Design Engineer for the most cutting-edge work. Synapse Design assists its clients in developing their next generation flagship product lines (mobile devices, complex routers/switches, consumer products, storage, microprocessor, graphics
processors etc.). This includes developing cutting edge technologies that are key and rare in the industry. We offer a fun, creative and flexible work environment.
As a Staff RTL Design Engineer, you will work with different teams like microarchitecture, SOC, GPU teams to implement the designs meeting aggressive power, area and performance goals using industry standard tools/flows.
10+ years of experience in SoC design Experience i
Contact :
Job Description:
  • Implement algorithm blocks as RTL code as defined in the Micro Architecture
  • Support DV team for verification of blocks
  • Assist with synthesis and timing closure
  • Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and
  • Primetime is required. 
  • Preferred Qualifications 10+ years of experience in SoC design
  • Support handoff and integration of blocks into larger SOC environments
  • Ability to document and communicate clearly
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Design Verification Engineer

Post date :11/16/2022
Job Duties:
Job Responsibilities
  • Develop and implement test/verification plans, methodologies and tool flows for graphics/display IPs
  • Define and implement IP/SubSystem verification plans, test benches and simulation/emulation coverage leading to fully functional IPs/SubSystems/SoCs
  • Drive DV plan development and execution through post-silicon bringup/validation
  • Define and implement system/integration tests
  • Work with cross functional teams to identify best verification methodology
  • Build or leverage highly automated & flexible DV environments/flows spanning prototypes, SoC’s and hardware emulation platforms
  • Support integration of IP block tests into larger SubSystem or SoC environment tests
Minimum Qualifications
  • 5+ years of similar experience in Design Verification using System Verilog
  • Experience with SystemVerilog UVM testbenches, coverage analysis, and SVA
  • Experience with FPGA and SoC design flows, tools and methodology
  • Experience with industry standard RTL simulators, emulators and waveform debugging tools
  • Capable of dealing with ambiguity with a fast changing consumer electronics field.
  • Results oriented, self-motivated, proactive with demonstrated creative & critical thinking
Preferred Qualification
  • Experience in GPU, Display, or Imaging Pipeline Silicon development.
  • Experience in development System Verilog UVM testbench environment from scratch
  • Experience with Software/Hardware Co-simulation (DPI/VPI)
  • Experience with C/C++ modeling of the Hardware Systems
  • Experience with verification of high speed interfaces like MIPI
  • Experience with on-chip bus protocols (AXI, AXI-Lite, AHB, OCP)
  • Experience with post-silicon lab/bench test/validation
5+ years of experience in Design Verification
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RTL Design Engineer

Post date :11/16/2022
Job Duties:
  • Verilog/System Verilog experience is must.
  • Experience with AMBA Bus protocol (AXI/AHB/APB) is must.
  • Experience with Front End tools (simulation, lint, cdc) is required
  • Experience with image/Video processing is desirable.
  • Experience with Datapath/control logic is desirable.
  • Ability to quickly provide simulation debug support
  • Good scripting skills is desirable.
RTL Design Engineer : Synapse Design Inc.  United States (Remote)  
Contact :
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Senior Emulation Engineer

Post date :11/16/2022
Job Duties:
Job Description
Build emulation models for ASIC designs at the SoC and IP level - FPGA prototyping for ASIC design at the IP level. - Develop transactors for emulation models. - Automation support for emulation build and release - Triage and debug emulation test fails. - Familiar with emulation platform Zebu - Familiar with FPGA prototyping - Good programming skills in C/C++, Python, shell scripting
Senior DFT Engineer
5+ years industry experience required
Contact :
Skill Set:  BS or above in electrical engineering or computer engineering
  • Experience with Hierarchical DFT Architecture
  • Experience using Synopsys or Mentor test tools.
  • Experience in Scan Insertion, test Muxing, ATPG, MBist & pre/post-layout simulation
  • Expertise in Top Level DFT switching with DFT Architecture experience will add value
  • Expertise in test clock strategy & muxing required
  • Expertise in test timing constraints for shift, capture, mbist or any special mode & timing closure for these modes
  • Familiar with low power testability, state tables, and components (LS, ISO, RET)
  • Familiar with JTAG for board level interconnect testing
  • Programming experience in Tcl & Perl is must
  • Involvement in flow development is a plus
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