The leading SOC and ASIC design services company
Current Openings

Browse through the current openings at Synapse Design and apply. Post your resumes in easy steps to join the Synapse Design team and be agent of innovation.

Select Country

Design For Test Engineer

Post date :06/29/2022
Job Duties:
  •  Architecting and Designing the entire DFT architecture of the design
  • Develop the customized STEM based DFT methodologies for the project
  • Scan insertion, Scan Compression insertion, Power aware ATPG, analyzing & fixing design rule checks (DRC).
  • Block level and SOC level pattern generation and Simulation with advanced faults models including stuck-at, Transition, IDDQ, Path delay, Cell-aware etc.
  • Hierarchical clock controller implementation
  • Implicit chains to be implemented to integrate the external logics to the core
  • On chip controller implementation to facilitate at-speed testability
  • Coverage analysis on low Test coverage with Stuck-at, Transition and other fault models
  • Spyglass Test point insertion for test cost reduction
  • Developing STA (Static Timing Analysis) constraints for DFT circuitry
  • Static and Dynamic timing analysis & optimization
  • Pattern porting flow development to cut short design cycle and ATPG runtime
  • Diagnostics and Post silicon debugging, root cause analysis (RCA)
  • Boundary Scan Insertion (Bscan), pattern generation and verification to test for IEEE 1149.1 compliance
  • Memory built in self-test (MBIST) & Programmable BIST insertion, memory test vector creation, simulation and failure debugging
  • Develop the STEM based validation environment to simulate all the DFT circuitry.
  • Contact :

    To apply please mention Job Code S05 and mail resumes to: Attn. Rosheni Fernando, Director Finance and Administration, Synapse Design Automation, Inc., 2200 Laurelwood Rd, Santa Clara, CA 95054.