VERIFICATION

Synapse Design assists large organizations in migrating to the latest and greatest approaches in UVM/OVM/VMM verification tools and methodologies. We help our Customers develop their next complex chip, eliminating functional bugs long before tapeout, saving significant time and money on respins.

Design Services:

• Verification plan and methodology definition
• Test coverage and test plan development
• Testbench analysis, development and implementation
• Block/ Chip level verification
• Code and functional coverage planning, analysis and closure
• Cache Coherency and AXi 3/4 related verification
• Upgrade of Customer verification environment to new UVM/OVM/VMM based methodology

Areas of Expertise:

• Verification Methodologies: UVM, OVM, VMM, RVM, eRM
• HVL based verification
• C/Assembly based SOC – Co-simulation and verification
• Constrained random verification
• Coverage driven verification planning and closure
• Assertion based verification
• Formal verification
• Power Aware verification
• Hardware assisted verification
  • Emulation
  • FPGA

Primary Tools:

• Partnerships with all major tools vendors
• System Verilog based UVM, OVM and VMM Methodology
• Specman based eRM Methodology
• Vera based RVM Methodology
• Verilog/ VHDL
• ARM C and Assembly based