PHYSICAL DESIGN/SYNTHESIS

With the Synapse state-of-the-art design methodology, our highly skilled engineering teams, and our proven track record of successful tapeouts, Synapse is the only place to come for Physical Design support. We have taped out devices down to 28nm, closed timing on devices with clocks rate >>1.5Ghz, worked with chips having > 100 million gates and achieved utilization metrics which exceeded our Customers expectations

Design Services:

• Top level Design Analysis and planning
• Power distribution and clock planning
  • Floorplanning
  • DFT Insertion
  • Design for Manufacturability
  • Design for Power
  • Place & Route
  • Clock distribution (CTS, HTree etc.) and analysis
  • Scan restitching
  • Synthesis
  • Timing closure - MCMM
  • AOCV/Hold Margin
  • Physical verification (DRC/LVS)
  • Tapeout process

Areas of Expertise:

• High performance chips: > 1.5GHz and > 400sq.mm in 28nm, 32nm SOI & 40nm
• Optimization of SOCs for power & performance – Graphics Processors, Networking ASICs, Mobile ASICs, Storage, DSP & Video SOCs & Custom Designs Low Power Design [Multiple Power Domain/ Power Islanding]
• Design for Cost [Die Reduction vs Performance]
• Timing Closure – SSTA, MCMM, SI/AOCV/ Crosstalk
• High Routability & Utilization
• Low Skew Clock distribution network
• DFM & MFY

Primary Tools:

• Magma (Blast)
• Synopsys (Jupiter, Astro, StarRC-XT, Formality, ICC, PT-SI)
• Cadence (Celtic, Encounter, Verplex, VoltageStorm, Virtuoso  
• Mentor (Calibre)
• Apache (Redhawk)

Synthesis/Timing/Analysis:

• Chip/block level synthesis
• Constraint generation and debug
• Static timing analysis and repair
• SI/Timing closure
• Timing paths
• Multi-clock domain
• Hierarchical/chip level synthesize
• Crosstalk/noise analysis
• EM/IRDrop analysis
• RC extraction
• Power/clock analysis

Tools:

• Design Compiler, Physical Compiler, IC Compiler, Blast-create, BlastRTL, Primetime, PT-SI, Magma*, Hspice, Celtic, Scripting languages such as TCL, Python, Perl and UNIX shell