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- Chip/block level synthesis
- constraint generation and debug
- static timing analysis and fixing
- SI/Timing closure
- Timing paths
- Multi-clock domain
- Hierarchical/chip level synthesize
- Crosstalk/noise analysis
- EM/IRDrop analysis
- RC extraction
- power/clock analysis
- Design Compiler, Physical Compiler, IC Compiler, Blast-create,
BlastRTL, Primetime, PT-SI, Magma*, Hspice, Celtic, Scripting languages
such as TCL, Perl and UNIX shell.
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