To apply, please send your resume
to:
careers@synapse-da.com
Please send resumes as word-formatted
attachments.
Phone number is 408
850-3640.
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Responsibilities:
- Specify the DFT architecture for chips in development
including JTAG functionality, boundary scan, hierarchical scan, at-speed
testing, I/O testing requirements, memory BIST and repair, and analog
IP testing.
- Design and implement test logic
- Generate and debug test patterns
and convert those patterns to atest program
- Work with the test engineers
to optimize the test program for volume manufacturing.
- Research and
make recommendation regarding new testing techniques, tools, and technologies
that improve product quality and/or manufacturing costs.
Requirements:
- BSEE with 5+ years of DFT experience
- Proficiency with tools such
as: LogicVision, Fastscan, Tetramax and/or Syntest.
- Verilog design,
simulation and debugging environments/tools, Perl, UNIX command shells,
and equivalence checking
- Expert in the areas
like ATPG, BIST, MBIST, Boundary Scan and JTAG TAP Controllers, and
test vector creation/generation
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