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Experience: 5-10 years
- RTL design, Synthesis, Static Timing Analysis, formal verification,
debug of RTL/gate-level simulation issues, ECO process, interface
with architectural and physical design teams
- System on Chip design experience
is required
- System architecture, understanding of high speed bus interfaces
and memory interfaces a definite plus
- Lab end to end Bring Up (initial to equal
to production) of
complicated ASICs a definite plus
Requirements:
- BS/MS in Electrical or Computer Engineering or related field
- Proven track
record of successful state-of-the-art ASIC designs from
design to production. in leading-edge technology
Send resume
to: careers@synapse-da.com
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