The leading SOC and ASIC design services company
Current Openings

Browse through the current openings at Synapse Design and apply. Post your resumes in easy steps to join the Synapse Design team and be agent of innovation.

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Senior Physical Design Engineer, Santa Clara CA

Post date :02/27/2019
Skill Set:
BS, MS in electrical engineering or computer engineering
Experience using Synopsys ICC/ICC2 or Cadence Innovus/SOC Encounter
Successful tapeout experience of multiple complex chips (10M+ gates) at 28 nm or below
Expertise in floorplanning, Physical Synthesis, CTS, Routing
Expertise in low power flow (power gating, multi-Vt, voltage islands, dynamic voltage scaling, body biasing, etc)
Hands on experience with STA using Primetime, power analysis, DRC/LVS, Noise analysis
Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.)
Programming experience in tcl, Perl or C
Experience :
6+ years
Job Description :
Responsible for place/route of complex SoCs in advanced process technologies
Define the floorplan, including pin placement, power busing, placement of blocks and macros
Design complex clocking structures
Execute place/route, signal integrity avoidance/fixing, power/clock analysis, timing closure, noise analysis and DRC/LVS

Senior Design For Test (DFT) Engineer, Santa Clara CA

Post date :02/27/2019
Skill Set:
BS, MS, PhD, in electrical or computer engineering
Expertise with tools for scan design, ATPG, Memory BIST and boundary scan is required
Experience with test tools and simulators from one or more EDA vendor is required
Experience working with multiple complex chips at 28 nm and below
Proficiency with Linux, Perl and TCL is required
Good problem solving and debugging skills
Experience :
Job Description :
Responsible across the full spectrum of Design For Test (DFT) solutions for complex chips on leading edge technologies
Insert scan, Memory BIST and boundary scan into designs, and create both ATPG and functional patterns
Run test suites and debug chips in test labs
Write tools and scripts in Perl and other scripting languages to enhance the DFT process
Work on complex high performance and low power designs

Senior Design Verification Engineer, Boston MA

Post date :02/27/2019
Skill Set:
BS, MS in computer science or engineering
Experience with SystemVerilog
Experience with the  UVM 
Experience with one or more simulators from the major EDA suppliers (Cadence, Mentor or Synopsys)
Experience with advanced verification techniques like constrained random generation, functional coverage, assertions and formal verifiers
Experience with tools for regression management, configuration management and bug tracking
Good software skills in object oriented programming (OOP), C, C++, Perl, tcl, csh
Good problem solving and debugging skills
Experience :
6+ years
Job Description :
Create verification plans for complex SOCs and IP blocks
Create testbenches in SystemVerilog with UVM
Utilize advanced verification techniques
Write tools and scripts in Perl and other script languages to enhance the verification process