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DFT Engineer

Post date :06/22/2018
Skill Set:

DFT Engineer

Job Code: DFT02

 

Synapse Design Automation, Inc. has an opening for Santa Clara, CA site.

 

Job Description:

 

• Experience in DFT Verification.

 

• Study the design architecture for integrated chips, create verification plans for complex SOCs and IP blocks including SCAN, MBIST, Scan Compression, ATPG Fault Simulation and at-speed testing.

 

• Contribute to development and deployment of DFT (design for test) methodologies and infrastructure in collaboration with software, circuit design, product development, design automation, and product engineering teams to enhance the verification process.

 

• Design and insert DFT logic including boundary SCAN, SCAN chains, DFT Compression, Logic BIST, and other DFT IP blocks, run RTL, gate, and gate with SDF simulations to confirm correct functionally of DFT logic.

 

• Integrate DFT analysis and insertion tools in the overall ASIC design flow, complete and verify all test design rules and test benches,implement test benches to apply stimulus and checks to verify SOC and IP blocks performance.

 

• Generate ATPG vectors, bring-up and debug patterns, resolve test pattern and coverage issues, support test engineering and operations through qualification, burn-in and production.

 

• Utilize advanced verification techniques to efficiently solve IC design verification issues, drive continuous improvement, negotiate and clearly communicate technical tradeoffs with a diverse cross-functional team.

 

• Responsible for DFT Verification and MBIST Insertion and Verification and MBIST Insertion and Verification.

 

• Perform chip design using ST Micro Memory BIST Insertion flow. Work in Scan Insertion and Scan Compression, ATPG and pattern simulations on IP and chip level.

 

• Conduct ATPG Low coverage Analysis and BSCAN and post silicon debug.

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Experience :
Job Description :
Special Requirements:

Job entails working with and requires Bachelor`s degree in Electronic Engineering, Computer Engineering, or equivalent with 5 years of experience including: Scan Insertion, Formality, ATPG, SpyGlass DFT Checks, SpyGlass MBIST, Synopsys VCS Cadence ET, Simvision. Employer will accept any suitable combination of education, training or experience. This should be read to mean that the employer requires: Bachelor`s degree in Electronic Engineering, Computer Engineering, or Equivalent with 5 years of experience in the job offered, DFT Verification Engineer, Module Lead Engineer, or Equivalent.

 

Relocation and travel to unanticipated locations within USA possible.

   

Send resume referencing Job Code to: Attn: HR, Synapse, 2200 Laurelwood Road, Santa Clara, CA 95054.  

Senior Design Verification Engineer

Post date :06/22/2018
Skill Set:

Senior Design Verification Engineer

Job Code: DVE01

 

Synapse Design Automation, Inc. has multiple openings for Santa Clara, CA site.

 

Job Description:

 

• Study the design architecture for integrated chip, create verification plans for complex Systems-on-chip (SOC)s and IP blocks.

 

• Contribute to development and deployment of IC design verification methodologies in collaboration with software, circuit design, product development, design automation, and product engineering teams, write tools and scripts in Perl or other script languages to enhance the verification process.

 

• Determine the parameters and create test benches in System Verilog, Verilog –A and Verilog-AMS with VMM, OVM, UVM based methodology and Object-Oriented Programming (OOP).

 

• Verify the test benches for the IC chip designs

 

• Develop ASIC Register Transfer Level (RTL) verification designs for complex logic blocks in SOC projects and collaborate with other RTL designers and test bench owners to fix bugs.

 

• Implement test benches to apply stimulus and checks to verify SOCs and IP blocks performance, utilize Verilog, Verilog-A, Verilog-AMS to stimulus and check circuits, create System Verilog functional coverage models for voltages and currents, and digital functional coverage.

 

• Develop dashboard and coverage and debug the code coverage for the next generation chip design.

 

• Utilize advanced verification techniques to efficiently solve IC design verification issues, drive continuous improvement, negotiate and clearly communicate technical tradeoffs with a diverse cross-functional team.

 

• May require travel and/or relocation to various unanticipated client sites throughout the USA.

Experience :
Job Description :
 Special Requirements:

 

Job entails working with and requires Masters or foreign academic equivalent in Systems Engineering, Electronic/Electrical Engineering, Computer Science, Computer Engineering or a related field with 3 years of experience with 3 years of experience

including: ASIC RTL/SOC Verification, System Verilog, Verilog, UVM, VMM, Object-Oriented Programming (OOP), Perl and functional verification at both block level and full chip.

 

Employer will accept any suitable combination of education, training or experience. This should be read to mean that the employer requires: Masters or foreign academic equivalent in Systems Engineering, Electronic/Electrical Engineering, Computer Science, Computer Engineering or a related field with 3 years of experience in the job offered or any Hardware/Design Engineering positions or related occupations.

 

This position may require travel and/or relocation to various unanticipated client sites throughout the USA.

 

Send resume referencing Job Code to: Attn: HR, Synapse, 2200 Laurelwood Road, Santa Clara, CA 95054.